1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor memory, more specifically, to a method for manufacturing a gate structure of a semiconductor memory.
2. Description of the Prior Art
In the traditional process for manufacturing a semiconductor memory, a contact structure is usually formed by a contact hole to make necessary electrical connection between relative parts. As shown in FIG. 1, a bit contact structure formed by a DRAM semiconductor memory process mainly comprises a substrate 11 usually formed of silicon, a conducting layer 12 usually formed of poly-silicon, a metal layer 13 usually formed of WSi, a protective layer 14 usually formed of SiN, an insulating layer 15, which is referred to a spacer in general and usually formed of silicon nitride, a barrier layer 16 usually formed of silicon nitride, an insulating layer 17 usually formed of BPSG, an insulating layer 18 usually formed of TEOS, and a metal layer 19 mainly consisting of W and TiN/Ti. In this structure, the conducting layer 12, metal layer 13 and protective layer 14 compose gates. The metal layer 19, which is generally referred to an M0 metal layer, is formed as a bit line, and is also filled into a bit contact hole to form a bit line contact.
However, in the process of forming the bit line contact hole, the shoulder portions of the protective layer 14 and insulating layer 15 of the gate are usually damaged to expose the metal layer 13, since the etching time is very long. Accordingly, an improper short circuit between the metal layers 13 and 19 occur. One of the improving methods is to partially remove a portion of the sides of the gate metal layer 13 to avoid the undesired contact with the metal layer 19, as shown in FIG. 1.
The method mentioned above may solve the short circuit problem, however, since the side of the gate metal layer 13 is partially removed, the insulating layer 15 and barrier layer 16 may indent inward, causing a void 171 formed between the gates when the insulating layer 17 is formed, as shown in FIG. 1. Accordingly, the insulation property is degraded, and the electrical performance of the whole structure is influenced. Therefore, a solution for overcoming this problem is necessary.